The present invention relates generally to integrated circuits, and more particularly to buffers such as complementary push-pull buffers.
Complementary push-pull buffers offer low output impedance to drive large capacitive or resistive loads. In some applications, it is desirable for a push-pull buffer to have extremely low output impedance, e.g., in order to drive a very large capacitance load or a very low resistance load, and low bias current, e.g., in order to conserve power.
FIG. 1 shows a schematic diagram of a conventional complementary push-pull buffer 100 that converts an input signal INPUT into an output signal OUTPUT. The push-pull buffer 100 has two main transconductance (GM) devices: N-type (e.g., NMOS) source transistor N30 and P-type (e.g., PMOS) sink transistor P50, both of which are configured as a complementary source-follower stage to drive output.
P-type source-follower biasing circuitry 110, consisting of P-type transistors P12, P14, and P16 and N-type transistor N18, biases the input signal INPUT to drive GM source device N30, while N-type source-follower biasing circuitry 120, consisting of N-type transistors N22, N24, and N26 and P-type transistor P28, biases the input signal INPUT to drive GM sink device P50.
Current-mirror source circuitry 140, consisting of P-type transistors P42, P44, and P46, is connected to GM source device N30 such that the input (master) stage (i.e., device P42) of the current-mirror source circuitry 140 is connected in series with GM source device N30, while the output (slave) stage (i.e., device P46) of the current-mirror source circuitry 140 is connected in parallel with the series combination of devices N30 and P42.
Similarly, current-mirror sink circuitry 160, consisting of N-type transistors N62, N64, and N66, is connected to GM sink device P50 such that the input (master) stage (i.e., device N62) of the current-mirror sink circuitry 160 is connected in series with GM sink device P50, while the output (slave) stage (i.e., device N64) of the current-mirror sink circuitry 160 is connected in parallel with the series combination of devices P50 and N62.
With this configuration, substantially all of the current that flows through GM devices N30 and P50 also flows through current-mirror master devices P42 and N62. Devices P14, N18, N24, P28, P44, and P66 are power-down devices that are only used to turn the buffer 100 off when it is not in use. When the buffer 100 is in use, devices P44 and N66 (as well as devices N18 and P28) remain off, while devices P14 and N24 remain on.
As known in the art, current mirrors in the output stage are used to reduce output impedance of the complementary source-follower stage. As indicated in FIG. 1, the devices used to implement each set of the current-mirror circuitry 140 and 160 are sized such that each mirrored, output-stage current is 60 times larger than the input-stage current. This relatively large multiplication factor is selected to provide an acceptably low level of output impedance for certain applications of the buffer 100.
Unfortunately, the large multiplication factor also increases the power consumption of the buffer 100. In the exemplary implementation of FIG. 1, since the main GM devices N30 and P50 draw 16 microamps (uA), the 60× multiplication factor means that the output stages of the current mirrors draw 960 uA, which may be too much power consumption for some applications of the buffer 100.